The new chip has been designed for specialized automatic speech recognition. The key design factor is that the chip only requires low power to operate it. With a current chip for voice recognition, which might be used in a cellphone, around 1 watt of power is required to activate the software. With the new chip a far lower level of power is required; between 0.2 and 10 milliwatts. The actual power required is dependent upon the number of words the software needs to recognize.
If the chip can become commercialized this means in practice power savings of between 90 to 99 percent. This means the option of voice control would become practical for even the simplest of electronic devices. This could be a key development given that voice activation is one of the pillars for connected devices that will make up the so-called “Internet of Things.” This refers to vehicles, appliances, manufacturing equipment, and items in the home being equipped with sensors designed to report information directly to networked servers.
According to the lead scientist behind the low-power chip, Professor Anantha Chandrakasan (Massachusetts Institute of Technology): “Speech input will become a natural interface for many wearable applications and intelligent devices.”
He explains further that “the miniaturization of these devices will require a different interface than touch or keyboard. It will be critical to embed the speech functionality locally to save system energy consumption compared to performing this operation in the cloud.”
Voice recognition has advanced considerably in the past few years and tends to be based on neural networks, virtual networks of simple information processors roughly modeled on the human brain. The limitation is with the amount of power required to drive the devices. This is what the new chip addresses. This is achieved through bandwidth management. This is achieved through minimizing the chip’s memory bandwidth, which compresses the weights associated with each node. This allows the data to become decompressed only after it is brought onto the chip. The chip brings in a single node of the neural network at a time and efficiently passes the data from 32 consecutive 10-millisecond increments through it.
The new chip has yet to be published in a peer reviewed journal, although it has been presented to the recent International Solid-State Circuits Conference, in February 2017.
